Semiconductor power component and a method of producing same

ABSTRACT

A semiconductor power component and a method for producing a semiconductor power component, in particular a vertical NPT-IGBT for ignition applications with a breakdown voltage of less than approx. 1000 V. The semiconductor power component includes a wafer substrate of a first conductive type including a rear-side emitter region of a second conductive type and a front-side drift region of the first conductive type; a rear-side anode contact which is connected to the emitter region and extends partially to the front-side surface; a front-side MOS control structure; and a front-side cathode contact which is connected to a front-side source region and a body region of the front-side MOS control structure. The thickness of the drift region is much larger than the width of the space charge region at a defined breakdown voltage; and the thickness of the rear-side emitter region is greater than 5 μm.

FIELD OF THE INVENTION

The present invention relates to a semiconductor power component and amethod of producing a semiconductor power component.

BACKGROUND INFORMATION

Although applicable to other similar semiconductor power components, thepresent invention and the problems on which it is based are describedhere with respect to a vertical IGBT (insulated gate bipolartransistor).

In general, IGBTs are used as power circuit-breakers in a cutoff voltagerange from a few hundred volts to a few thousand volts. In particular,the use of such IGBTs as an ignition transistor, i.e., as a switch onthe primary side of an ignition coil, is of particular interest.

The structure of a vertical IGBT resembles that of a VDMOS transistor,except that a p⁺ emitter is arranged on its anode side instead of an n⁺substrate as in the VDMOS transistor. German Published PatentApplication No. 31 10 230 discusses a vertical MOSFET component havingthe basic structure of a vertical IGBT. In principle, two types ofvertical IGBT or V-IGBT are differentiated, namely the punch-throughIGBT (PT) and the non-punch-through IGBT (NPT), as discussed by Laska etal., Solid-State Electronics, volume 35, no. 5, pages 681-685, forexample.

The basic properties of these two types of IGBTs are described belowwith reference to FIGS. 2 and 3.

FIG. 2 shows a schematic cross-sectional diagram of an NPT-IGBT whoseactive region 10 includes cellular or strip-shaped MOS control heads 13,14, 15, 16, 17. In particular, this shows a p-type body region 13, an n⁺source 14, a p⁺ contact diffusion 15 for connecting p-type body region13 to a cathode terminal 19, which is connected at the same time to n⁺source region 14 and is at ground; there is also a gate electrode 16 anda gate oxide 17. In addition, there is an n-drift region 12, a p-emitter11 on the rear side and an anode terminal 18; “d” denotes the thicknessof p⁺ emitter 11 and 101 is a space charge region formed at the pnjunction between p-type body region 13 and n-drift region 12.

The NPT-IGBT according to FIG. 2 may be produced on a low-doped n⁻substrate having a long charge carrier lifetime. After penetration ofthe diffusion profiles on the front side VS of the wafer to create MOScontrol heads 13, 14, 15, 16, 17, p⁺ emitter 11 is produced in a veryshallow form with only a few μm depth of penetration (d≈few μm) and pooremitter efficiency on the rear side RS of the wafer. This transparentemitter region 11 has the function of ensuring a rapid shutdown of thecurrent in dynamic operation of this component, with the goal ofminimizing shutdown losses. To obtain satisfactory transmissionproperties despite such a poor emitter region 11, the carrier lifetimein the n⁻ drift region 12 must be as high as possible. Furthermore, thethickness of n⁻ drift region 12 is to be as small as possible, takinginto account the desired blocking ability of the component. As a resultof this, very thin wafers must be processed, especially in the range ofblocking abilities of around 1 kV. This is a highly complex procedureand has become possible only in recent years (see, for example, T. Laskaet al., Conf. Proc. ISPSD '97, pages 361-364).

FIG. 3 shows a schematic cross-sectional diagram of a PT-IGBT whoseactive region 20 includes cellular or strip-shaped MOS control heads 23,24, 25, 26, 27. In particular, this shows a p-type body region 23, an n⁺source region 24, a p⁺ contact diffusion 25 for connecting p-type bodyregion 23 to a cathode terminal 29, which is connected at the same timeto n⁺ source region 24; there is also a gate electrode 26 and a gateoxide 27. In addition, there is an n⁻ drift region 22 a and an n⁻ bufferregion 22 b, a p⁺ emitter 21 on the rear side and an anode terminal 28;201 denotes a space charge region formed at the pn junction betweenp-type body region 23 and n⁻ drift region 22 a.

The PT-IGBT according to FIG. 3 may be produced on a thick p⁺-dopedsubstrate, which at the same time forms rear-side emitter region 21,with epitactically applied n-buffer region 22 b and epitacticallyapplied n⁻ drift region 22 a. Since the thickness of n⁻ drift region 22a is selected to be lower than required by the width of space chargeregion 201 in the drift region at the desired blocking ability toachieve the lowest possible on-state voltage drop, n-buffer region 22 bhas the function of preventing the space charge region from extendingthrough to p⁺ emitter 21. To be able to achieve a rapid shutdown of thecurrent despite good emitter 21, the charge carrier lifetime is keptsmall by lifetime killing, e.g., by electron bombardment, and/or thedoping in n-buffer region 22 b is selected to be high accordingly. Theon-state voltage becomes higher with an increase in the buffer dose, soa good compromise may be achieved between the on-state voltage and theshutdown performance when using a highly doped thin buffer region 22 b.Such as buffer is feasible only to a limited extent in the production ofcrude wafers using such a double EPI/substrate wafer due to bufferoutward diffusion.

Therefore, there have been studies of PT-IGBTs on SDB (silicon directbonding) wafers such as that already published by C. Yun et al., Conf.Proc. ISPSD '98, pages 261-264. With these SDB wafers, a buffer implantis introduced into an n⁻ wafer of FZ silicon, and then this wafer isbonded directly to a p⁺ wafer of CZ silicon and healed. The resultingSDB crude wafer having the layer sequence n⁻n⁺p⁺ is then ground to thestandard thickness and forms the starting basis for the production ofPT-IGBTs according to the standard methods of semiconductor technology.This procedure may provide that with such SDB wafers, it is possible toproduce very thin buffer regions having a high doping.

In an article by K. D. Hobart et al., 1999 Proc. IEEE, pages 45-49, anNPT-IGBT on SDB wafer material is discussed. In this case, however, thecomponent is first produced on a standard n⁻ wafer of FZ siliconincluding metallization. The bonding process with the method discussedthere is complex and is performed following thin grinding of the waferin a low-temperature process (T<450° C.) so as not to damage the IGBTstructure which has already been metallized. Either an identical IGBTwafer or a p⁺ wafer is used as the bonding partner.

A brief explanation of the functioning of the IGBT types described hereis given below.

For the on-state case with both types of IGBTs, gate electrode 16 or 26is brought to a potential above the threshold voltage of MOS controlheads 13, 14, 15, 16, 17 or 23, 24, 25, 26, 27, respectively, withrespect to cathode terminal 19 or 29. Then an inversion channel isproduced on the semiconductor surface beneath gate terminal 16 or 26 inthe area of p-type body region 13 or 23. The semiconductor surface inthe region of n⁻ drift region 12 or 22 a is then in the condition ofaccumulation. When there is a positive voltage at anode terminal 18 or28 with respect to the cathode, electrons are injected into body regions13 or 23 via n⁺ source regions 14 or 24, the MOS channels thusinfluenced, and the accumulation layer is injected into n⁻ drift region12 or 22 a.

Then anode-side emitter region 11 or 21 injects holes through which n⁻drift region 12 or 22 a is flooded with charge carriers so that itsconductivity is increased. It is in the high injection phase at on-statecurrent densities. Therefore, an IGBT having a blocking ability aboveapprox. 150-200 V is capable of carrying higher current densities havinga lower voltage drop between the anode and cathode than a MOS transistorhaving the same breakdown voltage. In the on-state case, the currentflows from the anode to the cathode. It is carried by electrons whichare injected into n⁻ drift region 12 or 22 a and flow out via anode-sideemitter 11 or 21 to the anode and by holes which are injected by theanode-side emitter into n⁻ drift region 12 or 22 a and flow toward thecathode via p-type regions 13, 15 or 23, 25.

In the blocking case, gate electrode 16 or 26 is brought to a voltagebelow the threshold voltage with respect to cathode terminal 19 or 29.If anode terminal 18 or 28 is then brought to a positive potential, thenspace charge region 101 or 201 arranged between p-type body region 13 or23 and n⁻ drift region 12 or 22 a expands almost exclusively into n⁻drift region 12 or 22 a.

In the case of NPT-IGBT, the thickness of n⁻ drift region 12 is selectedto be larger than the width of space charge region 101 at a givenmaximum blocking ability of the component.

With the PT-IGBT, the thickness of n⁻ drift region 22 a is selected tobe smaller than the width of the space charge region at a given maximumblocking ability of the component. To prevent space charge region 201from running over onto p⁺ emitter region 21, n-doped buffer region 22 bis introduced with the goal of preventing said punch-through.

FIG. 4 shows a circuit topology of another system in which a verticalIGBT 30′ is used as an ignition transistor in the primary circuit of anignition coil for an internal combustion engine. For this application asan ignition transistor having the required blocking capacities ofapprox. 400-600 V, so far only PT-IGBTs on double EPI/substrate crudewafers have been used, thereby avoiding the problems of thin wafers withNPT-IGBTs as described above.

According to FIG. 4, vertical IGBT 30′ is connected to battery voltage33 across an ignition coil 31. A spark plug 32 is provided on thesecondary side of ignition coil 31. A diode 37 which is connected tocontrol terminal 38 provides ESD protection, and resistors 35, 36 (e.g.,where R36=1 kΩ and R35=10-25 kΩ) define the input resistance of theconfiguration as well as form the load of a clamping diode chain 34.Elements 30, 34, 35, 36, 37 may be monolithically integrated, diodes 37,34 normally being made of polysilicon.

The circuit configuration according to FIG. 4 is operable directly by asuitable control unit via control terminal 38. To do so, a positivevoltage of 5 V, for example, is applied to control terminal 38,whereupon a current increase is initiated through ignition coil 31. At acertain point in time, the voltage at control terminal 38 is reduced inincrements to approx. 0 V, whereupon the voltage at node 39 increasessteeply. This voltage increase is stepped up on the secondary side ofignition coil 31 and results in an ignition spark at spark plug 32.

Clamping diode chain 34 has the function of limiting the voltage rise atanode 39 to what is called the terminal voltage of approx. 400 V toprotect IGBT 30′ and also to protect the other circuit components. Thisis important in particular in the pulse case which occurs, for example,when no ignition spark is generated, e.g., due to an ignition cablehaving fallen off. Then IGBT 30′ has to absorb the energy otherwiseconverted in the spark. Without such a voltage limitation, the anodevoltage at node 39 would increase to the point of breakdown of IGBT 30′and would destroy it. This is prevented by clamping diode chain 34 bythe fact that on reaching a preselected terminal voltage, the gate ofIGBT 30′ is triggered just strongly enough to prevent the voltage fromexceeding the terminal voltage at node 39. Nevertheless, this operatingcase makes high demands on the pulse strength of IGBT 30′ due to thehigh energy converted, and it is not always possible to ensure thesedemands will be met to an adequate extent. The negative consequencewould be destruction of IGBT 30′.

J. Yedinak et al., Conf. Proc. ISPSD, 1998, pages 399-402 have shownthat a failure consequently occurs, as described in conjunction withFIG. 5.

FIG. 5 shows a schematic cross-sectional diagram of a PT-IGBT whoseactive region 40 includes cellular or strip-shaped MOS control heads 43,44, 45, 46, 47. In particular, this shows a p-type body region 43, an n⁺source region 44, a p⁺ contact diffusion 45 for connecting p-type bodyregion 43 to a cathode terminal 49, which is connected at the same timeto n⁺ source region 44; this also shows a gate electrode 46 and a gateoxide 47. In addition, there is an n⁻ drift region 42 a and an n-bufferregion 42 b, a rear-side p+emitter 41 and an anode terminal 48; 401denotes a space charge region formed at the pn junction between p-typebody region 43 and n⁻ drift region 42 a.

In the pulse case, space charge region 401 covers entire n⁻ drift region42 a. Electrons 402 are injected via the MOS channel that has developedin p-type body region 43 into n⁻ drift region 42 a, triggering p⁺emitter 41 via a triggering of the gate controlled by said clampingdiodes. Gain factor β of the pnp transistor formed by regions 41, 42 a,42 b, 43 is higher at a high voltage than in the on state (see Takei etal., Conf. Proc. ISPSD, 1999, Appendix Paper 7.1), which is why a lowtriggering voltage at gate terminal 46 is sufficient to carry the loadcurrent and thus to limit the anode voltage to the terminal voltage. Dueto the power loss which thus occurs, the component becomes very hot atthe cathode in particular, whereupon an electron leakage current occurs.Electrons 403 run in the direction of the anode and control bias p⁺emitter region 41 there. They thus act like an additional triggering ofthe IGBT. To keep the voltage at the level of the terminal voltage,triggering of gate terminal 46 is reduced via the terminal diode chainaccordingly. Under certain operating conditions, the triggering due tothe thermally induced electron leakage current is so strong that theIGBT is able to carry the load current without any gate control. Itscontrollability is lost. The temperature increases further and theleakage current also increases further, ultimately resulting in positivethermal feedback and destruction of the IGBT.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a rugged IGBT forignition applications in particular, so that the IGBT will have goodon-state properties and a high pulse strength and will be easilyprocessable.

The semiconductor power component according to the present invention mayprovide that a rugged IGBT is made available without the need forprocessing thin wafers.

The present invention provides for a wafer substrate of a firstconductive type including a rear-side emitter region of a secondconductive type and a front-side drift region of the first conductivetype, the thickness of the drift region being much greater than thewidth of the space charge region at a defined breakdown voltage, and thethickness of the rear-side emitter region being greater than 5 μm.

According to an exemplary embodiment, the breakdown voltage is less than1000 V, the thickness of the drift region between the front-side MOScontrol structure and the rear-side emitter region being greater than200 μm.

According to another exemplary embodiment, the rear-side emitter regionis a diffusion region.

According to another exemplary embodiment, the substrate is an SDBsubstrate.

According to another exemplary embodiment, the rear-side emitter regionis an epitaxy region.

According to another exemplary embodiment, the thickness of the driftregion between the front-side MOS control structure and the rear-sideemitter region is at least 20 μm greater than the width of the spacecharge region at the defined breakdown voltage.

According to another exemplary embodiment, the thickness of the driftregion between the front-side MOS control structure and the rear-sideemitter region is selected so that the temperature increase in therear-side emitter region up to the point in time at which the front sidehas reached a defined maximum temperature in the pulse case does notexceed a value of approx. 50 K.

According to another exemplary embodiment, the first conductive type isthe n type, and the second conductive type is the p type.

According to another exemplary embodiment, the drift region has acarrier lifetime of more than 10 μs in the high injection case.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic cross-sectional diagram of a vertical NPT-IGBTaccording to one exemplary embodiment of the present invention.

FIG. 2 shows a schematic cross-sectional diagram of a NPT-IGBT ofanother system.

FIG. 3 shows a schematic cross-sectional diagram of a PT-IGBT of anothersystem.

FIG. 4 shows a circuit topology of another system in which a verticalIGBT is used as the ignition transistor in the primary circuit of anignition coil for an internal combustion engine.

FIG. 5 shows a schematic cross-sectional diagram of a NPT-IGBT ofanother system to illustrate a failure mechanism.

DETAILED DESCRIPTION

The same reference numbers in the figures denote the same components orthose having the same function.

FIG. 1 shows a schematic cross-sectional diagram of a vertical NPT-IGBTaccording to exemplary embodiment of the present invention.

FIG. 1 shows an active region 50 of an NPT-IGBT and a corresponding n⁻p⁺substrate 51, 52. This substrate 51, 52 is either an n⁻ wafer substrateincluding a rear-side p⁺ diffusion or an n⁻p⁺ SDB crude wafer or an n⁻wafer substrate including a rear-side p⁺ epitaxy layer.

As mentioned above, n⁻ drift region 52 in said n⁻p⁺ substrate is theknown drift region in active region 50 of the IGBT, and p⁺ rear side 51is the anode-side emitter.

FIG. 1 shows in particular a cross section through a cell and/or a stripwithin the active region of the IGBT without the passivation layerswhich are referred to in other systems. The entire active region may beobtained by monolithic integration of a plurality of such cells, i.e.,strips side by side. The edge closure and/or the required clamp circuitaccording to FIG. 4 are executable according to the related art and areintegratable into a chip together with the active region.

FIG. 1 also shows an anode contact 58, i.e., anode metallization on rearside RS of the wafer and a cathode contact 59, i.e., cathodemetallization on front side VS of the wafer. Cathode contact 59electrically connects regions 54 and 55 and/or 54′ and 55′ to eachother. In this connection, 54, 54′ denotes a front-side n⁺ source regionand 55, 55′ a respective p⁺ contact diffusion for connecting p-type bodyregion 53, 53′ beneath it. A gate electrode 56 may be made ofpolysilicon is electrically insulated by a gate oxide 57 a from thesemiconductor surface and by an intermediate dielectric 57 b fromcathode contact 59. p⁺ regions 55, 55′ are not only p⁺ contactdiffusions for electric connection of p-type body regions 53, 53′ tocathode contact 59 but they also suppress latch-up. One inversionchannel may be formed by a positive gate voltage on the surface of eachof p-type body regions 53, 53′. n⁺ source regions 54, 54′ are used toresupply the electrons injected in the on state and/or the clamp casethrough the inversion channels into the low-doped n⁻ drift region 52.The thickness of n⁻ drift region 52 between the MOS control region andrear-side p⁺ emitter region 51 is selected to be much larger thanrequired by the width of the space charge region in n⁻ drift region 52at a defined, i.e., desired breakdown voltage of typically 400-600 V inignition applications, e.g., 20 μm thick or more.

On the rear side of the wafer, p⁺ emitter region 51 is provided with adepth d greater than 20 μm. The high p⁺ doping provides ohmic contactbinding of emitter 51 to rear-side anode contact 58. The IGBT accordingto this exemplary embodiment is manufacturable by standard manufacturingmethods of semiconductor technology. The thickness of the crude wafermust not be less than for rear-side-diffused bipolar transistors ofother systems despite the typical breakdown voltage of down to approx.400 V. Therefore, no methods yielding very thin wafer thicknesses ofless than 200 μm are necessary during the entire manufacturing process.

In the manufacture of this IGBT, first the front-side diffusions,oxides, metals, and cover layers are produced in/on the p⁺n⁻ substrate.Following that, rear side RS of the wafer is cleaned and conditioned,e.g., by a grinding and/or etching operation. The required amount ofmaterial to be removed will vary depending on the substrate used. Forexample, in the case of an RSD wafer, the amount of material to beremoved will be as small as possible (a few μm), in the case of an SDBwafer it will be large (a few 100 μm), and in the case of an EPI/SUBwafer it will be small (a few μm). Finally, rear-side metallization 58is applied. For precision equalization of the properties of the presentIGBT, it is possible to introduce a targeted adjustment of the carrierlifetime, e.g., by electron bombardment.

In the finished IGBT, n⁻ substrate region 52 of the crude wafer formsthe drift region of the IGBT, and p⁺ region 51 minus the layer removedduring cleaning/conditioning forms the rear-side emitter. Use of an n⁻substrate having a long carrier lifetime in combination with the deep p⁺emitter region results in good conducting properties superior to thoseof comparable previous NPT-IGBTs including a transparent emitter. Due tothe long carrier lifetime (more than 10 μs at high injection) achievablein the substrate in comparison with an n⁻ layer produced epitactically,the on-state voltage drop in the IGBT according to the present exemplaryembodiment is as expected lower than with a comparably doped NPT-IGBT ona p⁺ substrate including an n⁻ epitaxy layer as the drift region.

In comparison with the NPT-IGBT on an SDB crude wafer discussed byHobart et al., the present NPT-IGBT is simpler to manufacture. Since itis possible to start with a crude wafer having a standard waferthickness (e.g., 700 μm) that has already been bonded, this eliminatesthe low-temperature bonding of thinned partially processed wafers. Inaddition, high-temperature methods of other systems may be used in themanufacture of the SDB crude wafers.

The shutdown behavior of the IGBT according to the present exemplaryembodiment is not critical in the ignition application. First, a rapidsubsidence of the anode current after shutting down the device voltageis not necessary as in other applications, but instead the anode voltagemust be run up within times of less than a few 10 μs with the leastpossible dependence on temperature. On the other hand, the maximumswitching frequency is approximately two orders of magnitude smaller incomparison with other applications. The high pulse strength of the IGBTaccording to the present exemplary embodiment results from the followingfacts. Due to the great thickness selected for n⁻ drift region 52, thecurrent gain factor β of the pnp transistor formed by regions 51, 52, 53and/or 53′ is low even at a high off-state voltage. In addition, withcomparable drift region doping, the field distribution in the NPT-IGBTis more favorable than in the PT-IGBT. The applied off-state voltage maybe picked up at lower field strengths because the extent of the spacecharge region is not limited by a buffer. Therefore, the MOS controlheads in the NPT-IGBT are heated to a lesser extent than in the PT-IGBT.The effect of positive feedback described above on the example of thePT-IGBT according to the related art via a thermally-induced electronleakage current therefore occurs only at higher loads on the componentin the pulse case.

In addition, the thick n⁻ drift region may also be used for achieving ahigh pulse strength for another reason. It is known that the (gain)properties of an emitter may increase with an increase in temperature.This may not be desirable from the standpoint of a high pulse strength.An increase in gain results in a lower (thermally induced) leakagecurrent, resulting in loss of controllability of the IGBT, than would bethe case with temperature-independent gain. Therefore, the goal is toexpose such emitters to no increase in temperature, which is achieved bya thick n⁻ drift region. In the pulse case, by far the greatest powerloss occurs and thus heat is lost to the cathode side of the IGBT. Theheat front requires a certain amount of time to reach the emitter. Thistime depends on the distance between the cathode side of the IGBT andthe p⁺ emitter. It may be adjusted through the choice of a thick n⁻drift region so that heating of the emitter during the critical phase inthe pulse case remains slight and increases only thereafter.

Although the present invention has been described above on the basis ofan exemplary embodiment, it is not limited to this but instead ismodifiable in a variety of manners.

For example, if the types of doping and the polarity of the voltage tobe applied are swapped, this yields a corresponding p-channel NPT-IGBTfrom the n-channel NPT-IGBT. In general, this is superior to then-channel NPT-IGBT with regard to latch-up strength but is inferior withregard to avalanche strength.

1. A method of producing a semiconductor power component, the methodcomprising: preparing a wafer substrate of a first conductive type,including a rear-side emitter region of a second conductive type and afront-side drift region of the first conductive type; providing afront-side MOS control structure, including a front-side source regionand a body region which are introduced into the front-side and a controlcontact, arranged as an insulated contact above the body region andabove a part of the front-side drift region adjoining thereto; removinga portion of material of a rear side of the wafer substrate by at leastone of an etching operation and a grinding operation; providing arear-side anode contact connected to the rear-side emitter region andextending partially to the front-side; and providing a front-sidecathode contact that is connected to a front-side source region of thefront-side MOS control structure and the body region; wherein athickness of the front-side drift region between the front-side MOScontrol structure and the rear-side emitter region is considerablylarger than a width of a space charge region at a defined breakdownvoltage, and a thickness of the rear-side emitter region is greater than5 μm, the thickness of the front-side drift region being of suchdimension that a temperature increase in the rear-side emitter region upto a point in time at which the front-side has reached a defined maximumtemperature in a pulse case does not exceed a value of approximately50K.
 2. The method of claim 1, wherein the rear-side emitter regionincludes a diffusion region and the rear-side diffusion is performedbefore producing the front-side MOS control structure.
 3. The method ofclaim 2, wherein a penetration of depth of the rear-side diffusion ismore than 20 μm and removal of the portion of material on the rear sideis a few μm.
 4. The method of claim 2, wherein the lifetime of thecharge carriers is adjusted by one of bombardment and alifetime-reducing implantation.
 5. The method of claim 1, wherein thewafer substrate includes an SDB substrate, and the removal of thematerial on the rearside of the wafer substrate is such that theremaining thickness of the rear-side emitter region is greater than 20μm.
 6. The method of claim 1, wherein the rear-side emitter region is anepitaxy region having a thickness greater than 5 μm, and the rear-sideepitaxy is performed before providing the front-side MOS controlstructure.
 7. A semiconductor power component comprising: a wafersubstrate of a first conductive type, including a rear-side emitterregion of a second conductive type and a front-side drift region of thefirst conductive type; a rear-side anode contact connected to therear-side emitter region and extending partially to the front-side driftregion; a front-side MOS control structure, including front-side sourceregion and a body region which are introduced into the front-side driftregion, and a control contact, arranged as an insulated contact abovethe body region and above a part of front-side the drift regionadjoining thereto; and a front-side cathode contact connected to thefront-side source region and the body region; wherein a thickness of thefront-side drift region between the front-side MOS control structure andthe rear-side emitter region is considerably larger than a width of thespace charge region at a defined breakdown voltage, and a thickness ofthe rear-side emitter region is greater than 5 μm, the thickness of thefront-side drift region being of such dimension that a temperatureincrease in the rear-side emitter region up to point in time at whichthe front-side has reached a defined maximum temperature in a pulse casedoes not exceed a value of approximately
 50. 8. The semiconductor powercomponent of claim 7, wherein the defined breakdown voltage is less than1000 V, and the thickness of the front-side drift region between thefront-side MOS control structure and the rear-side emitter region isgreater than 200 μm.
 9. The semiconductor power component of claim 7,wherein the rear-side emitter region includes a diffusion region. 10.The semiconductor power component of claim 7, wherein the wafersubstrate includes an SDB substrate.
 11. The semiconductor powercomponent of claim 7, wherein the rear-side emitter region includes anepitaxy region.
 12. The semiconductor power component of claim 7,wherein the thickness of the front-side drift region between thefront-side MOS control structure and the rear-side emitter region is atleast 20 μm greater than the width of the space charge region at thedefined breakdown voltage.
 13. The semiconductor component powercomponent of claim 7, wherein the first conductive type is a p-type andthe second conductive type is a n-type.
 14. The semiconductor powercomponent of claim 7, wherein the front-side drift region has a carrierlifetime of more than 10 μs in high injection case.